1. Field of Invention
The present invention relates to an analog-to-digital converter. More particularly, the present invention relates to a pipelined analog-to-digital converter.
2. Description of Related Art
Electronics systems, such as communication or imaging systems, often require a high-speed, high-resolution analog-to-digital converter (ADC) core that can be operated at a low supply voltage and at low power-consumption levels. A switched-capacitor pipeline ADC architecture is one common implementation of a high-speed, high-resolution ADC core. In general, an ADC usually utilizes switched capacitors for sampling and holding a signal in order to achieve a high sampling rate.
In the conventional pipelined ADC, the input stages include a sample-and-hold (SAH) circuit, typically a switched-capacitor circuit, and an multiplying digital to analog converter (MDAC) block as the first residue stage (or the first stage) of the pipelined ADC. While a pipelined SAR ADC architecture realizes high resolution analog-to-digital conversion, such a SAR ADC architecture requires additional processing time for the SAR ADC, and the operational amplifier thereof becomes more difficult to design.
Therefore, there is a need for a new pipelined ADC which consumes less power and has an improved the timing performance.